Avoiding the loss of data stored in the memory cells of a semiconductor memory during a power shutdown is an important problem in memory design and use. Such a power shutdown may be anticipated sufficiently far in advance to allow time to transfer the data from the memory cells to a separate non-volatile storage location in the memory--i.e., a storage location which does not require power for preserving the data. Commonly, however, shutdown occurs without adequate warning to allow data transfer to the separate non-volatile location. It is therefore desirable to incorporate a non-volatile storage site directly in each cell.
In "A 256-Bit Nonvolatile Static RAM," 1978 IEEE ISSCC Dig. of Tech. Papers, Feb. 16, 1978, pp. 108-9, E. Harari et al. disclose a memory cell for achieving the foregoing objective. In this static RAM cell, a pair of cross-coupled P-channel FET's form a volatile random-access location for storing a data bit. The P-channel FET's are individually connected through their drains to the drains of a pair of cross-coupled variable-threshold floating-gate N-channel FET's which form a non-volatile storage location. Just prior to a power shutdown, the cell power supply is raised from its normal value of 5-10 volts up to about 20 volts for 10 microseconds. This places the non-volatile location in a state indicative of the data bit contained in the volatile location. In particular, the threshold voltage of one of the N-channel floating-gate FET's goes to a positive value while the threshold voltage of the other floating-gate FET goes to an opposing negative value. When the power is shut down, the P-channel FET's both turn off to cause the bit in the volatile storage location to "evaporate". However, the threshold voltages of the N-channel FET's remain at their opposing values. As power is restored, the opposing threshold voltages of the N-channel FET's cause the complement of the original data bit to appear in the volatile location. B. Troutman et al. disclose substantially the same arrangement in FIG. 2b of U.S. Pat. No. 4,128,773, except that the FET polarities are reversed. In either of these non-volatile RAM cells, an additional pair of FET's serve as a load circuit.
In U.S. Pat. No. 4,095,281 with particular reference to FIG. 2, G. Denes discloses another memory cell that appears to operate in basically the same manner as that of Harari et al. or Troutman et al. The principal difference is that Denes uses P metal-nitride-oxide semiconductor (MNOS) FET's for the variable-threshold FET's and does not use an additional pair of FET's in the load circuit.
Although these prior art devices provide non-volatile data storage, none of them return the original data bit to the volatile storage locations in the memory cells when power is restored. Instead, a separate operation must normally be performed to invert the complement data to get back the data in its original form. This is undesirable since it requires further time and/or circuitry.
In "A Single 5 V Supply Nonvolatile Static RAM," 1981 IEEE ISSCC Dig. of Tech. Papers, Feb. 19, 1981, pp. 148-9, J. Drori et al. disclose a non-volatile RAM cell that avoids the inconvenience of having the complement of the original data bit returned to the cell after a power shutdown. This cell requires at least six FET's in addition to a triple polycrystalline silicon floating-gate structure for preserving the original data bit during shutdown and, consequently, is relatively complex.